Forbes

SiFive Is Leading The Way For Innovation On RISC-V

The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...
TechNewsWorld

ClearSpeed Unveils Multithreaded Array Processor

ClearSpeed Technology, a provider of low-power chip-based systems, has unveiled the CS301 processor, a multithreaded chip designed to improve performance and reduce power consumption for ...
Geeky Gadgets

RISC-V Vector Processing: A New Era in Computing Efficiency

The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...
Semiconductor Engineering

RISC-V decoupled Vector Processing Unit (VPU) For HPC

A technical paper titled “Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications” was published by researchers at Barcelona Supercomputing Center ...
EDN

The next RISC-V processor frontier: AI

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
Semiconductor Engineering

Computational SRAM (C-SRAM) Solution Combining In- and Near-Memory Computing Approaches

New academic paper titled “Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution”, from researchers at Univ.